Monitoring device, motor driving apparatus, and monitoring method

ABSTRACT

A monitoring device includes: an acquisition unit for acquiring a clock signal output from a communication circuit that outputs the clock signal; and a monitoring unit for analyzing the waveform of the clock signal acquired by the acquisition unit, based on a predetermined reference clock signal having a period equal to or shorter than a period of the clock signal to thereby determine whether or not there is a sign of malfunction in the communication circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2019-231439 filed on Dec. 23, 2019, thecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a monitoring device, a motor drivingapparatus, and a monitoring method.

Description of the Related Art

Japanese Laid-Open Patent Publication No. 2004-173380 discloses a motorcontrol device including a plurality of microcomputers for controllingmotors. In Japanese Laid-Open Patent Publication No. 2004-173380, eachmicrocomputer reads the electric current value of the associated motorat a timing that is shifted from the timings when switching signals areoutput from the other microcomputers. Thus, in Japanese Laid-Open PatentPublication No. 2004-173380, the influence of switching noise can beavoided.

SUMMARY OF THE INVENTION

However, Japanese Laid-Open Patent Publication No. 2004-173380 cannotdetect a sign of malfunction of the communication circuit due to theinfluence of noise and the like.

It is therefore an object of the present invention to provide amonitoring device, a motor driving apparatus, and a monitoring method,capable of detecting a sign of malfunction in a communication circuit.

According to one aspect of the present invention, there is provided amonitoring device, including: an acquisition unit configured to acquirea clock signal output from a communication circuit that outputs theclock signal; and a monitoring unit configured to analyze a waveform ofthe clock signal acquired by the acquisition unit, based on apredetermined reference clock signal having a period equal to or shorterthan a period of the clock signal, and thereby determine whether or notthere is a sign of malfunction in the communication circuit.

According to another aspect of the present invention, there is provideda motor driving apparatus including the above monitoring device, themotor driving apparatus further including: an inverter configured tosupply an electric current to a motor; a current detector configured todetect the electric current supplied to the motor; and a control unitconfigured to control the inverter. In the motor driving apparatus, thecommunication circuit is configured to output the clock signal and datacorresponding to a detection signal detected by the current detector, tothe control unit, and the control unit is configured to output thereference clock signal to the monitoring unit.

According to another aspect of the present invention, there is amonitoring method including: an acquisition step of, with an acquisitionunit, acquiring a clock signal output from a communication circuit thatoutputs the clock signal; and a monitoring step of, with a monitoringunit, determining whether or not there is a sign of malfunction in thecommunication circuit, by analyzing a waveform of the clock signal,based on a predetermined reference clock signal having a period that isequal to or shorter than a period of the clock signal.

According to the present invention, it is possible to provide amonitoring device, a motor driving apparatus, and a monitoring method,capable of grasping a sign of malfunction in a communication circuit.

The above and other objects, features, and advantages of the presentinvention will become more apparent from the following description whentaken in conjunction with the accompanying drawings in which a preferredembodiment of the present invention is shown by way of illustrativeexample.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a motor driving apparatusaccording to an embodiment;

FIG. 2 is a time chart showing a clock signal and a reference clocksignal;

FIG. 3 is a time chart showing an example of a state in which thevoltage level of the clock signal is kept at a high level due to theinfluence of disturbance noise, or the like;

FIG. 4 is a time chart showing an example of a state in which thevoltage level of the clock signal is kept at a low level due to theinfluence of aging deterioration of a communication circuit, or thelike;

FIG. 5 is a flowchart showing an operational example of a monitoringdevice according to the embodiment;

FIG. 6 is a flowchart showing an operational example of a monitoringdevice according to the embodiment;

FIG. 7 is a time chart showing a clock signal and a reference clocksignal; and

FIG. 8 is a time chart showing an example of a state in which thevoltage level of the clock signal is kept at the high level due to theinfluence of disturbance noise, or the like.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A monitoring device, a motor driving apparatus, and a monitoring methodaccording to preferred embodiments of the present invention will bedescribed, in detail, below with reference to the accompanying drawings.

Embodiment

A monitoring device, a motor driving apparatus, and a monitoring methodaccording to an embodiment will be described with reference to FIGS. 1to 6. FIG. 1 is a diagram showing a configuration of a motor drivingapparatus according to the present embodiment.

A motor driving apparatus 10 according to the present embodiment candrive a motor 12.

The motor driving apparatus 10 includes an inverter (inverter unit) 14that supplies electric current to the motor 12. The inverter 14 includesan unillustrated converter circuit, an unillustrated capacitor, and anunillustrated inverter circuit. The converter circuit converts AC(alternate current) voltage supplied from an AC power supply 15 into DC(direct current) voltage. The capacitor smooths the DC voltage rectifiedby the rectifier circuit provided in the converter circuit. The invertercircuit can drive the motor 12 by converting the DC voltage suppliedfrom the converter circuit into an AC voltage and supplying the ACvoltage to the motor 12.

The motor driving apparatus 10 further includes a control unit 16. Thecontrol unit 16 controls the entire motor driving apparatus 10. Thecontrol unit 16 may be configured by, for example, a processor such as aCPU (Central Processing Unit), but is not limited to this. The controlunit 16 can control the inverter 14. The control unit 16 can drive themotor 12 by appropriately switching the switching elements (powerelements) provided in the inverter circuit and the like. The controlunit 16 may output an after-mentioned reference clock signal RCLK to amonitoring unit 22, which will be described later.

The motor driving apparatus 10 further includes a current detector 18.The current detector 18 is disposed between the inverter 14 and themotor 12. The current detector 18 detects an electric current suppliedfrom the inverter 14 to the motor 12. The current detector 18 outputs adetection signal corresponding to the current supplied from the inverter14 to the motor 12, to a communication circuit 20, which will bedescribed later.

The motor driving apparatus 10 further includes a communication circuit20. The communication circuit 20 outputs data D corresponding to thedetection signal supplied from the current detector 18, to the controlunit 16. That is, the communication circuit 20 outputs the data Dindicating the current supplied to the motor 12 from the inverter 14, tothe control unit 16. The communication circuit 20 outputs the data D tothe control unit 16 based on a clock signal CLK. The communicationcircuit 20 outputs not only the data D but also the clock signal CLK, tothe control unit 16.

The motor driving apparatus 10 further includes a monitoring device 24.The monitoring device 24 includes an acquisition unit 21 and amonitoring unit 22. The acquisition unit 21 and the monitoring unit 22can be configured by, for example, a processor such as a CPU, but arenot limited to this. The acquisition unit 21 can acquire the clocksignal CLK output from the communication circuit 20. The monitoring unit22 can analyze the waveform of the clock signal CLK acquired by theacquisition unit 21. The monitoring unit 22 can analyze the waveform ofthe clock signal CLK by using a predetermined reference clock signalRCLK having a period T2 (see FIG. 2), which is equal to or shorter thanthe period T1 of the clock signal CLK (see FIG. 2). The reference clocksignal RCLK can be supplied from, for example, the control unit 16, butis not limited to this.

When there is a sign of malfunction in the communication circuit 20 dueto the influence of disturbance noise, aging deterioration of thecommunication circuit 20, and the like, the waveform of the clock signalCLK may get into a state different from the normal state. The monitoringunit 22 can analyze the waveform of the clock signal CLK to determinewhether or not there is a sign of malfunction in the communicationcircuit 20. When the analyzed waveform of the clock signal CLK isdifferent from a predetermined basic waveform, the monitoring unit 22determines that there is a sign of malfunction in the communicationcircuit 20. The basic waveform is a waveform of the clock signal CLK inthe normal state, that is, the waveform of the clock signal CLK that isnot affected by disturbance noise or the like.

The monitoring unit 22 can analyze the waveform of the clock signal CLKby observing (detecting) the voltage levels of the clock signal CLK atrising timings or falling timings of the reference clock signal RCLK.That is, the monitoring unit 22 observes the voltage level of the clocksignal CLK at rising or falling timings of the reference clock signalRCLK, and thereby can determine whether or not the analyzed waveform ofthe clock signal CLK is different from the predetermined basic waveform.

FIG. 2 is a time chart showing the clock signal and the reference clocksignal. FIG. 2 shows an example in which the period T2 of the referenceclock signal RCLK is set shorter than the period T1 of the clock signalCLK. Here, for description convenience, an example is shown in which theperiod T2 of the reference clock signal RCLK is one-fourth of the periodT1 of the clock signal CLK. From the viewpoint of analyzing the clocksignal CLK with higher accuracy, it is preferable that the period T2 ofthe reference clock signal RCLK is sufficiently shorter than the periodT1 of the clock signal CLK. FIG. 2 shows an example in which the voltagelevel of the clock signal CLK is observed at rising timings of thereference clock signal RCLK.

In the example shown in FIG. 2, the reference clock signal RCLK rises attiming t1. When the timing is generally described, a reference numeral tis used, and when individual timings are described, reference numeralst1, t2, t3, . . . are used. The monitoring unit 22 observes (detects)the voltage level of the clock signal CLK at the timing t1. In theexample shown in FIG. 2, the voltage level of the clock signal CLK atthe timing t1 is L, i.e., a low level.

The reference clock signal RCLK rises at a timing t2, which is a timingoccurring one cycle (period T2) after the timing t1. The monitoring unit22 observes the voltage level of the clock signal CLK at the timing t2.In the example shown in FIG. 2, the voltage level of the clock signalCLK at the timing t2 is H, i.e., a high level.

The reference clock signal RCLK rises at a timing t3, which is a timingoccurring one period T2 after the timing t2. The monitoring unit 22observes the voltage level of the clock signal CLK at the timing t3. Inthe example shown in FIG. 2, the voltage level of the clock signal CLKat the timing t3 is H.

The reference clock signal RCLK rises at a timing t4, which is a timingoccurring one period T2 after the timing t3. The monitoring unit 22observes the voltage level of the clock signal CLK at the timing t4. Inthe example shown in FIG. 2, the voltage level of the clock signal CLKat the timing t4 is L.

The reference clock signal RCLK rises at a timing t5, which is a timingoccurring one period T2 after the timing t4. The monitoring unit 22observes the voltage level of the clock signal CLK at the timing t5. Inthe example shown in FIG. 2, the voltage level of the clock signal CLKat the timing t5 is L.

After this, the monitoring unit 22 also observes the voltage level ofthe clock signal CLK at rising timings t6, t7, t8, and t9 of thereference clock signal RCLK in the same manner as described above. Inthe example shown in FIG. 2, the voltage levels of the clock signal CLKat the timings t6, t7, t8, and t9 are H, H, L, and L, respectively.

Thereafter, the monitoring unit 22 also observes the voltage levels ofthe clock signal CLK at rising timings t10, t11, t12, and t13 of thereference clock signal RCLK in the same manner as described above. Inthe example shown in FIG. 2, the voltage levels of the clock signal CLKat the timings t10, t11, t12, and t13 are H, H, L, and L, respectively.

When the period T2 of the reference clock signal RCLK is one-fourth ofthe period T1 of the clock signal CLK, the voltage level of the clocksignal CLK observed at the rising timings t of the reference clocksignal RCLK repeats the above-described cycle of H, H, L, L. When thevoltage level of the clock signal CLK sequentially observed at therising timings t of the reference clock signal RCLK repeats the cycle ofH, H, L, L, the monitoring unit 22 can determine that the waveform ofthe clock signal CLK is the same as the predetermined basic waveform.

There are cases where the voltage level of the clock signal CLK may bekept at the high level or the low level due to the influence ofdisturbance noise or the like. Since the communication circuit 20outputs data D according to the clock signal CLK, if the clock signalCLK is kept at the high level or the low level, there is a risk that thedata D cannot be output correctly. That is, when the voltage level ofthe clock signal CLK is kept at the high level or the low level, thereis a possibility that the communication circuit 20 is malfunctioning.

FIG. 3 is a time chart showing an example of a state in which thevoltage level of the clock signal is kept at the high level due to theinfluence of disturbance noise or the like. Though FIG. 3 shows anexample of a state in which the voltage level of the clock signal CLK iskept at the high level due to the influence of disturbance noise or thelike, the clock signal CLK may be kept at the low level due to theinfluence of a disturbance noise or the like. In the example shown inFIG. 3, the observed voltage levels of the clock signal CLK at thetimings t1 to t7 are the same as those in the example shown in FIG. 2.However, in the example shown in FIG. 3, the level of the clock signalCLK observed at the timing t8 is H. As described above, in the exampleshown in FIG. 2, the level of the clock signal CLK observed at thetiming t8 is L. Thus, in the example shown in FIG. 3, the level of theclock signal CLK observed at the timing t8 differs from that in theexample shown in FIG. 2. The level of the clock signal CLK observed atthe timing t8 in the case shown in FIG. 3 becomes different from thecase shown in FIG. 2 because of the influence of disturbance noise orthe like that occurred during a time period between the timing t7 andthe timing t8 in the example shown in FIG. 3. In the example shown inFIG. 3, the voltage levels of the clock signal CLK observed after thetiming t9 are the same as those in the example shown in FIG. 2.

In the example shown in FIG. 2, the voltage levels of the clock signalsCLK observed at the timings t6 to t9 are H, H, L, L, respectively. Onthe other hand, in the example shown in FIG. 3, the voltage levels ofthe clock signals CLK observed at the timings t6 to t9 are H, H, H, L,respectively. That is, in the example shown in FIG. 3, the waveform ofthe clock signal CLK is not the same as the predetermined basicwaveform. Since the waveform of the clock signal CLK is not the same asthe predetermined basic waveform, the monitoring unit 22 determines thatthere is a sign of malfunction in the communication circuit 20.

FIG. 4 is a time chart showing an example of a state in which thevoltage levels of the clock signal are kept at the low level due to theinfluence of aging deterioration of the communication circuit or thelike. Though FIG. 4 shows an example in which the voltage levels of theclock signal CLK are kept at the low level due to the influence of agingdeterioration of the communication circuit 20 or the like, there arecases where the voltage levels of the clock signal CLK are kept at thehigh level due to aging deterioration of the communication circuit 20 orother. In the example shown in FIG. 4, the voltage levels of the clocksignal CLK observed at the timings t1 to t9 are the same as those in theexample shown in FIG. 2. However, in the example shown in FIG. 4, thelevels of the clock signal CLK observed at the timing t10 and thereafterare L, L, L, L, . . . . As described above, in the example shown in FIG.2, the levels of the clock signal CLK observed at the timing t10 andthereafter are H, H, L, L, . . . . Thus, in the example shown in FIG. 4,the levels of the clock signal CLK observed at the timing t10 andthereafter are different from those in the example shown in FIG. 2. Thelevels of the clock signal CLK observed at the timing t10 and thereafterbecome different from the cases shown in FIGS. 2 and 3 because theinfluence of aging deterioration of the communication circuit 20 or thelike has occurred after the timing t8 in the example shown in FIG. 4.

In the example shown in FIG. 2, the voltage levels of the clock signalCLK observed at the timings t10 to t13 are H, H, L, L, respectively. Onthe other hand, in the example shown in FIG. 4, the voltage levels ofthe clock signal CLK observed at the timings t10 to t13 are L, L, L, L,respectively. That is, in the example shown in FIG. 4, the waveform ofthe clock signal CLK is not the same as the predetermined basicwaveform. Since the waveform of the clock signal CLK is not the same asthe predetermined basic waveform, the monitoring unit 22 determines thatthere is a sign of malfunction in the communication circuit 20.

An operational example of the monitoring device 24 according to thepresent embodiment will be described with reference to FIG. 5. FIG. 5 isa flowchart showing an operational example of the monitoring deviceaccording to the present embodiment.

At step S1, the communication circuit 20 outputs data D according to theclock signal CLK and also outputs the clock signal CLK. Step S1 iscontinuously performed.

At step S2, the monitoring unit 22 analyzes the waveform of the clocksignal CLK based on the reference clock signal RCLK. Step S2 iscontinuously performed.

At step S3, the monitoring unit 22 determines whether or not theanalyzed waveform of the clock signal CLK is different from thepredetermined basic waveform. When the analyzed waveform of the clocksignal CLK is different from the predetermined basic waveform (YES atstep S3), the process proceeds to step S4. When the analyzed waveform ofthe clock signal CLK is not different from the predetermined basicwaveform (NO at step S3), the process proceeds to step S5.

At step S4, the monitoring unit 22 determines that there is a sign ofmalfunction in the communication circuit 20. Thus, the process shown inFIG. 5 is completed.

At step S5, the monitoring unit 22 determines that there is no sign ofmalfunction in the communication circuit 20. Thus, the process shown inFIG. 5 is completed.

The monitoring unit 22 may determine that there is a sign of malfunctionin the communication circuit 20 when a time period during which thevoltage level of the clock signal CLK is kept at H or L is equal to orlonger than a time threshold Tth. When the clock signal CLK is normal,the time period during which the clock signal CLK is kept at H or L ishalf the period of the clock signal CLK. The time threshold Tth can beset to a value obtained by adding a certain margin to half the period ofthe clock signal CLK. The start of the time period during which theclock signal CLK is kept at H is, for example, a timing at which themonitoring unit 22 detects that the voltage level of the clock signalCLK has transitioned from L to H. The end of the time period duringwhich the clock signal CLK is kept at H is, for example, a timing atwhich the monitoring unit 22 detects that the voltage level of the clocksignal CLK has transitioned from H to L. The start of the time periodduring which the clock signal CLK is kept at L is, for example, a timingat which the monitoring unit 22 detects that the voltage level of theclock signal CLK has transitioned from H to L. The end of the timeperiod during which the clock signal CLK is kept at L is, for example, atiming at which the monitoring unit 22 detects that the voltage level ofthe clock signal CLK has transitioned from L to H.

An operational example of the monitoring device 24 according to thepresent embodiment will be described with reference to FIG. 6. FIG. 6 isa flowchart showing an operational example of the monitoring deviceaccording to the present embodiment. FIG. 6 shows an example in which itis determined that there is a sign of malfunction in the communicationcircuit 20 when the time period during which the voltage level of theclock signal CLK is kept at the high level or the low level is equal toor longer than the time threshold Tth.

At step S1, the communication circuit 20 outputs data D according to theclock signal CLK and outputs the clock signal CLK. Step S1 iscontinuously performed.

At step S2, the monitoring unit 22 analyzes the waveform of the clocksignal CLK based on the reference clock signal RCLK. Step S2 iscontinuously performed.

At step S11, the monitoring unit 22 determines whether or not the timeperiod during which the voltage level of the clock signal CLK is kept atH or L is equal to or longer than the time threshold Tth (i.e., whetherthe time period Tth). When the time period during which the voltagelevel of the clock signal CLK is kept at H or L is equal to or longerthan the time threshold Tth (YES at step S11), the process proceeds tostep S4. When the time period during which the voltage level of theclock signal CLK is kept at H or L is shorter than the time thresholdTth (NO at step S11), the process proceeds to step S5.

At step S4, the monitoring unit 22 determines that there is a sign ofmalfunction in the communication circuit 20. Thus, the process shown inFIG. 6 is completed.

At step S5, the monitoring unit 22 determines that there is no sign ofmalfunction in the communication circuit 20. Thus, the process shown inFIG. 6 is completed.

As described theretofore, in the present embodiment, the waveform of theclock signal CLK is analyzed using the predetermined reference clocksignal RCLK having the period T2 that is equal to or shorter than theperiod T1 of the clock signal CLK. When the analyzed waveform of theclock signal CLK is different from the predetermined basic waveform, itis determined that there is a sign of malfunction in the communicationcircuit 20. Thus, according to the present embodiment, it is possible toadvantageously grasp the presence or absence of a sign of malfunction inthe communication circuit 20.

(Modification)

A monitoring device according to a modification of this embodiment willbe described with reference to FIGS. 7 and 8. FIG. 7 is a time chartshowing a clock signal and a reference clock signal.

In this modification, the period T2 of the reference clock signal RCLKis set to be equal to the period T1 of the clock signal CLK. In thismodification, the voltage level of the clock signal CLK is observed(detected) at rising timings and falling timings of the reference clocksignal RCLK.

As shown in FIG. 7, the reference clock signal RCLK rises at a timingt21. A reference numeral t is used to generally describe the timing, andreference numerals t21, t22, t23, . . . are used to describe individualtimings. The monitoring unit 22 observes the voltage level of the clocksignal CLK at the timing t21. In the example shown in FIG. 7, thevoltage level of the clock signal CLK at the timing t21 is H, that is,the high level.

The reference clock signal RCLK falls at a timing t22, which is a timingoccurring half the period ((T2)/2) after the timing t21. The monitoringunit 22 observes the voltage level of the clock signal CLK at the timingt22. In the example shown in FIG. 7, the voltage level of the clocksignal CLK at the timing t22 is L, that is, the low level.

The reference clock signal RCLK rises at a timing t23, which is a timingoccurring half the period ((T2)/2) after the timing t22. The monitoringunit 22 observes the voltage level of the clock signal CLK at the timingt23. In the example shown in FIG. 7, the voltage level of the clocksignal CLK at the timing t23 is H.

The reference clock signal RCLK falls at a timing t24, which is a timingoccurring half the period ((T2)/2) after the timing t23. The monitoringunit 22 observes the voltage level of the clock signal CLK at the timingt24. In the example shown in FIG. 7, the voltage level of the clocksignal CLK at the timing t24 is L.

The reference clock signal RCLK rises at a timing t25, which is a timingoccurring half the period ((T2)/2) after the timing t24. The monitoringunit 22 observes the voltage level of the clock signal CLK at the timingt25. In the example shown in FIG. 7, the voltage level of the clocksignal CLK at the timing t25 is H.

Thereafter, the monitoring unit 22 also observes the voltage levels ofthe clock signal CLK at falling and rising timings t26, t27, t28, t29,and t30 of the reference clock signal RCLK in the same manner asdescribed above. In the example shown in FIG. 7, the voltage levels ofthe clock signal CLK at the timings t26, t27, t28, t29, and t30 are L,H, L, H, and L.

When the period T2 of the reference clock signal RCLK is equal to theperiod T1 of the clock signal CLK, the voltage level of the clock signalCLK observed at the rising and falling timings t of the reference clocksignal RCLK repeats the above-described cycle of H, L, H, L. When thevoltage level of the clock signal CLK sequentially observed at therising and falling timings t of the reference clock signal RCLK repeatsthe cycle of H, L, H, L, the monitoring unit 22 can determine that thewaveform of the clock signal CLK is the same as the predetermined basicwaveform.

As described above, there are cases where the voltage level of the clocksignal CLK may be kept at the high level or the low level due to theinfluence of disturbance noise, the influence of aging deterioration ofthe communication circuit 20 or the like. FIG. 8 is a time chart showingan example of a state in which the voltage level of the clock signal iskept at the high level due to the influence of disturbance noise or thelike. In the example shown in FIG. 8, the observed voltage levels of theclock signal CLK at the timings t21 to t23 are the same as those in theexample shown in FIG. 7. However, in the example shown in FIG. 8, thelevel of the clock signal CLK observed at the timing t24 is H. Asdescribed above, in the example shown in FIG. 7, the level of the clocksignal CLK observed at the timing t24 is L. Thus, in the example shownin FIG. 8, the level of the clock signal CLK observed at the timing t24differs from that in the example shown in FIG. 7. The level of the clocksignal CLK observed at the timing t24 in the case shown in FIG. 8becomes different from the case shown in FIG. 7 because of the influenceof disturbance noise or the like that occurred during the time periodbetween the timing t23 and the timing t24 in the example shown in FIG.8. In the example shown in FIG. 8, the voltage levels of the clocksignal CLK observed at the timing t25 and thereafter are the same asthose in the example shown in FIG. 7.

In the example shown in FIG. 7, the voltage levels of the clock signalsCLK observed at the timings t23 and t24 are H and L. On the other hand,in the example shown in FIG. 8, the voltage levels of the clock signalsCLK observed at the timings t23 and t24 are H and H. That is, in theexample shown in FIG. 8, the waveform of the clock signal CLK is not thesame as the predetermined basic waveform. Since the waveform of theclock signal CLK is not the same as the predetermined basic waveform,the monitoring unit 22 determines that there is a sign of malfunction inthe communication circuit 20.

In this way, the period T2 of the reference clock signal RCLK may be setto be equal to the period T1 of the clock signal CLK. With thismodification, it is possible to preferably grasp the presence or absenceof a sign of malfunction in the communication circuit 20.

Though the preferred embodiment of the present invention have beendescribed above, the present invention is not limited to the aboveembodiment, and various modifications can be made without departing fromthe gist of the present invention.

For example, the above embodiment has been described by giving anexample where the reference clock signal RCLK is supplied from thecontrol unit 16 to the monitoring unit 22, but the present invention isnot limited to this. For example, a clock oscillation circuit thatgenerates the reference clock signal RCLK may be provided in themonitoring unit 22.

The above embodiment is summarized as follows.

A monitoring device (24) includes: an acquisition unit (21) configuredto acquire a clock signal (CLK) output from a communication circuit (20)that outputs the clock signal; and a monitoring unit (22) configured toanalyze the waveform of the clock signal acquired by the acquisitionunit, based on a predetermined reference clock signal (RCLK) having aperiod (T2) equal to or shorter than a period (T1) of the clock signal,and thereby determine whether or not there is a sign of malfunction inthe communication circuit. This configuration makes it possible tosuitably grasp the presence or absence of a sign of malfunction in thecommunication circuit.

The monitoring unit may be configured to determine that there is a signof malfunction in the communication circuit when the analyzed waveformof the clock signal is different from a predetermined basic waveform.

The monitoring unit may be configured to analyze the waveform of theclock signal by observing the voltage level of the clock signal atrising or falling timings of the reference clock signal.

The monitoring unit may be configured to determine that there is a signof malfunction in the communication circuit when the time period duringwhich the voltage level of the clock signal is kept at the high level orthe low level is equal to or longer than a time threshold (Tth).

A motor driving apparatus (10) including the above-described monitoringdevice, further includes: an inverter (14) configured to supply anelectric current to a motor (12); a current detector (18) configured todetect the electric current supplied to the motor; and a control unit(16) configured to control the inverter. The communication circuit isconfigured to output the clock signal and data (D) corresponding to adetection signal detected by the current detector, to the control unit,and the control unit is configured to output the reference clock signalto the monitoring unit.

A monitoring method includes: an acquisition step (S1) of, with anacquisition unit, acquiring a clock signal output from a communicationcircuit that outputs the clock signal; and a monitoring step (S2 to S5)of, with a monitoring unit, determining whether or not there is a signof malfunction in the communication circuit, by analyzing the waveformof the clock signal, based on a predetermined reference clock signalhaving a period that is equal to or shorter than the period of the clocksignal.

The monitoring step may determine that there is a sign of malfunction inthe communication circuit when the analyzed waveform of the clock signalis different from a predetermined basic waveform.

The monitoring step may analyze the waveform of the clock signal byobserving the voltage level of the clock signal at rising or fallingtimings of the reference clock signal.

The monitoring step may determine that there is a sign of malfunction inthe communication circuit when a time period during which the voltagelevels of the clock signal is kept at a high level or a low level isequal to or longer than a time threshold.

The reference clock signal may be supplied from a control unitcontrolling an inverter that supplies an electric current to a motor, tothe monitoring unit.

What is claimed is:
 1. A monitoring device, comprising: an acquisitionunit configured to acquire a clock signal output from a communicationcircuit that outputs the clock signal; and a monitoring unit configuredto analyze a waveform of the clock signal acquired by the acquisitionunit, based on a predetermined reference clock signal having a periodequal to or shorter than a period of the clock signal, and therebydetermine whether or not there is a sign of malfunction in thecommunication circuit.
 2. The monitoring device according to claim 1,wherein the monitoring unit is configured to determine that there is asign of malfunction in the communication circuit when the analyzedwaveform of the clock signal is different from a predetermined basicwaveform.
 3. The monitoring device according to claim 2, wherein themonitoring unit is configured to analyze the waveform of the clocksignal by observing voltage level of the clock signal at rising orfalling timings of the reference clock signal.
 4. The monitoring deviceaccording to claim 3, wherein the monitoring unit is configured todetermine that there is a sign of malfunction in the communicationcircuit when a time period during which the voltage level of the clocksignal is kept at a high level or a low level is equal to or longer thana time threshold.
 5. A motor driving apparatus comprising the monitoringdevice according to claim 1, further comprising: an inverter configuredto supply an electric current to a motor; a current detector configuredto detect the electric current supplied to the motor; and a control unitconfigured to control the inverter, wherein: the communication circuitis configured to output the clock signal and data corresponding to adetection signal detected by the current detector, to the control unit;and the control unit is configured to output the reference clock signalto the monitoring unit.
 6. A monitoring method, comprising: anacquisition step of, with an acquisition unit, acquiring a clock signaloutput from a communication circuit that outputs the clock signal; and amonitoring step of, with a monitoring unit, determining whether or notthere is a sign of malfunction in the communication circuit, byanalyzing a waveform of the clock signal, based on a predeterminedreference clock signal having a period that is equal to or shorter thana period of the clock signal.
 7. The monitoring method according toclaim 6, wherein the monitoring step determines that there is a sign ofmalfunction in the communication circuit when the analyzed waveform ofthe clock signal is different from a predetermined basic waveform. 8.The monitoring method according to claim 7, wherein the monitoring stepanalyzes the waveform of the clock signal by observing voltage level ofthe clock signal at rising or falling timings of the reference clocksignal.
 9. The monitoring method according to claim 8, wherein themonitoring step determines that there is a sign of malfunction in thecommunication circuit when a time period during which the voltage levelof the clock signal is kept at a high level or a low level is equal toor longer than a time threshold.
 10. The monitoring method according toclaim 6, wherein the reference clock signal is supplied from a controlunit configured to control an inverter that supplies an electric currentto a motor, to the monitoring unit.